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Monolithic 3-D Integration of Logic and Memory: Carbon Nanotube FETs, Resistive RAM, and Silicon FETs

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December 17, 2014, IEDM, San Francisco—Max M. Shulaker from Stanford showed the integration of logic and memory in a 3-D IC using RRAM and carbon nano-tubes. The demonstration circuit is an FPGA routing element the combines the logic and memory functions.

Monolithic 3-D integration, whereby each circuit layer is thin and is fabricated directly over the previous circuit layers on the same substrate, can use conventional inter-layer vias (ILVs) to connect between various layers. The use of conventional vias rather than TSVs allows for massive vertical interconnect density, potentially maximizing the benefits of 3-D integrated circuits (ICs). Moreover, monolithic 3-D integration of logic and memory can enable new architectures and potentially alleviate the logic-memory communication bottleneck.

One of the challenges for 3-D ICs is the need for the processing temperatures for all upper layer circuitry must be low (<4000C), so as to not damage or destroy the lower layers of logic, memory, or metal interconnects. Previous work achieved monolithic 3-D integration of logic through the use of CNFETs due to their low processing temperature (<2500C), and with low-temperature wafer bonding of silicon SOI substrates. Monolithic 3-D integration of a layer of memory over a layer of logic has likewise been enabled by low-temperature RRAM processing.

To realize monolithic 3-D integration of logic and memory in arbitrary stacking order, we employ both CNFETs and RRAM as the upper-layers of logic and memory, while performing all fabrication on a starting silicon-FET substrate, thereby showing that the entire process is compatible with existing silicon technologies.

In addition to enabling monolithic 3-D integration, both CNFETs and RRAM are promising emerging nanotechnologies. CNFETs promise both improved performance and energy efficiency (~10x benefit in energy-delay product (EDP) compared to silicon-CMOS while RRAM potentially realizes a high-capacity storage and BEOL-compatible non-volatile memory.

The key enabler for monolithic 3-D integration of logic and memory elements is the use of emerging nanotechnologies with low processing temperatures over a starting silicon-FET substrate. We begin with the fabrication of conventional silicon-FETs as the first layer of logic, which may be used as an access transistor for the upper layers of RRAM. The high-temperature dopant activation rapid thermal anneal (10500C) is performed during the silicon-FET fabrication and before the fabrication of any circuitry on upper layers.

Following silicon-FET fabrication, a low-temperature (900C plasma-enhanced chemical vapor deposited (PECVD) 100 nm SiOX) inter-layer dielectric (ILD) is deposited, and inter-layer vias (ILVs) are etched and filled with metal. The 2nd layer of the 3-D IC (1st layer of RRAM cells) is deposited directly over this ILD. The RRAM uses a 10 nm Pt/ 5 nm HfOX/ 3 nm TiN/ 10 nm Pt stack, which is fabricated with maximum processing temperature of 2000C. The 3rd layer of the 3-D IC (2nd layer of RRAM cells) is fabricated in an identical manner, with an additional 100 nm ILD with ILVs connecting between the layers.

Following the 3rd vertical layer, a 3rd 100 nm ILD is deposited, in preparation for the 4th layer of the 3-D IC (2nd layer of logic using CNFETs). The CNTs are first grown on a crystalline quartz substrate, yielding >99.5 percent highly aligned CNTs. Following growth, the CNTs are transferred from the quartz growth substrate onto the 3-D IC, using a low-temperature (1300C) transfer process that maintains both the alignment and density of the CNTs.

This low-temperature transfer is essential, as it decouples the high temperature growth (~9000C) from the 3-D IC, which would otherwise damage or destroy both the bottom layers of logic, memory, and metal interconnects. To prepare the 3-D IC for CNT transfer, the ILD undergoes chemical-mechanical polishing (CMP) followed by an argon sputter etch to planarize the surface. The local bottom gates for the CNFETs (1 nm Ti/ 10 nm Pt) are patterned [9], followed by depositing the CNFET high-. gate dielectric (16 nm Al2OX) through atomic layer deposition (ALD) at 2000C. The CNTs are transferred onto the CNFET gate dielectric, followed by the CNFET source and drain definition (2 nm Ti/ 12 nm Pt).

We use the imperfection-immune paradigm to overcome the substantial imperfections inherent in CNTs: mis-positioned CNT-immune design renders the logic immune to mis-positioned CNTs, while VLSI-compatible Metallic CNT Removal (VMR) selectively removes >99.99 percent of the metallic CNTs from the circuit. Finally, ILVs connecting between any remaining vertical layers are etched and filled. Importantly, the fabrication of every layer is performed on the same starting substrate above the previous layers of logic and memory, in both a silicon-CMOS and VLSI-compatible manner.

To demonstrate the ability to connect between any two layers of logic and memory, we fabricate 1 transistor-1 RRAM (1T1R) structures between every possible combination of logic and memory in our monolithic 3-D stack. Scanning electron microscopy (SEM) images of each of the 1T1R structures across the different circuit layers shows the 1T1R structures for the 1st layer of silicon-FETs controlling the 1st and the 2nd layers of RRAM above them. Since none of the circuit layers are affected by the 3-D processing, the performance of both 1T1R structures are the same.

Both 1T1R structures involving different layers of the RRAM exhibit similar forming, reset, and set characteristics. Importantly, we confirm that the memory and logic performance is invariant to the fabrication order and placement in the 3-D IC stack. The difference in the set and reset curves between the 1T1R structures including the silicon-FET versus the CNFET is attributed to the CNFET not exhibiting the same saturation in the ID-VDS characteristics as the silicon-FET these CNFETs saturate at higher VDS due to un-optimized source and drain contact resistance, similar to previously reported ID-VDS CNFET characteristics.

The CNFET must be able to operate as a selector for the RRAM. As this is the first demonstration of CNFET and RRAM integration (in addition to monolithic 3-D integration of CNFETs and RRAM), we further characterize the CNFET’s ability to act as the selector for the RRAM. The CNFET can successfully be used to both set the compliance current for the set operation of the RRAM, and can be used as a pass-gate to select whether or not to perform the reset operation of the RRAM. These operations can be only performed after VMR is used to selectively remove >99.99 percent of the metallic CNTs, resulting in >5,000 ION/IOFF for the CNFET, while inadvertently removing <4 percent of the semiconducting CNTs and therefore retaining enough ION to perform the RRAM reset.

As an applied demonstration of monolithic 3-D integration of logic and memory, we fabricate a 4-layer switching element of a switchbox for an FPGA. Switchboxes for an FPGA implemented with RRAM-based configuration memory have been shown to save 40 percent in area and 28 percent in EDP, primarily attributed to the cell-size reduction due to the integration of RRAM over the silicon logic instead of the use of a 6T SRAM cell in silicon. With the ability to fabricate memory and logic on any arbitrary layer, both the RRAM select transistor and the routing transistor can be integrated on top of each other, further reducing the cell footprint.

Ideally, the routing element cell footprint can be further reduced to 4F2 The ION/IOFF is ~1000, which is attributed to the un-optimized silicon-FET fabrication with non-ideal threshold adjustment and inverse subthreshold slope. The fabricated switching element exhibits high switching endurance of >105 cycles with consistent programming voltages, suitable for FPGAs.
 


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